1. Field of the Invention
The present invention relates to a method for accessing a memory, especially to a method for accessing a one time programmable (OTP) memory.
2. Description of the Prior Art
Recently, non-volatile memories are widely adopted in all kinds of electronic products such as cell phones, digital cameras, and digital music players. These non-volatile memories are usually hard drives, flash memories, and OTP memories. Flash memories and OTP memories are two common types of memories. The major difference between these two kinds of memories is that a flash memory is refreshable while an OTP memory can only be written once. More specifically, a flash memory is capable of being read and written many times, but once an OTP memory is programmed, i.e., when some data are written into an OTP memory, the OTP memory can no longer be utilized to store another data.
A flash memory is a multi-time programmable (MTP) memory which is capable of being repeatedly written and erased, and therefore a flash memory requires some circuits that perform the erase, write, and read operations. However, an OTP memory requires only write and read operations but no erase operation; therefore, compared to an MTP memory, an OTP memory does not require a circuit to perform the erase operation. The simplicity of an OTP memory leads to a simpler and low-cost manufacturing process of the circuit of the OTP memory. Under a circumstance where only a few read and write processes are required, a plurality of OTP memories is often utilized to simulate an MTP memory. As a result, the performance of a MTP memory can be achieved without an additional erase circuit.
U.S. Pat. No. 6,728,137 discloses a method for performing the read and write operations on an OTP memory. A plurality of OTP memories is utilized to simulate an MTP memory. Please refer to FIG. 1. FIG. 1 shows a circuit configuration of a memory device. The memory device 100 contains an OTP memory area 110, a control circuit 120, a row decoder 130, a column decoder 140, and a record element 150. The OTP memory area 110 contains N OTP memory blocks 112, and every OTP memory block 112 contains a plurality of memory cells (not shown). Each memory cell stores a data of one bit. Since every memory cell is one time programmable, programmed memory cells cannot be written into new data, i.e., cannot be programmed again. The record element 150 consists of a plurality of record units 152, each of which contains one or more than one memory cell(s). Every record unit 152, which corresponds respectively to an OTP memory block 112, stores the usage status of its corresponding OTP memory block 112. For example, the record unit A stores the usage status of the OTP memory block #1, the record unit B stores the usage status of the OTP memory block #2, and so on. According to the embodiment disclosed in this patent, if some record unit 152 stores a data of “0”, the OTP memory block 112 corresponding to this record unit 152 is an un-programmed OTP memory block; however, if some record unit 152 stores a data of “1”, the OTP memory block 112 corresponding to this record unit 152 is a programmed OTP memory block. Please note that the minimum units of the OTP memory area 110 and the record element 150 are memory cells such that the same manufacturing method can be applied on both the OTP memory area 110 and the record element 150.
The control circuit 120, which is coupled to the record element 150, the row decoder 130, and the column decoder 140, outputs a control signal according to the data stored in the record element 150. After being decoded by the row decoder 130 and the column decoder 140, the control signal selects a proper OTP memory block 112 for being programmed or being read. Although the OTP memory blocks 112 contained in the OTP memory area 110 can only be programmed once and the stored data cannot be replaced by a new data, an MTP memory is able to be simulated by utilizing a plurality of OTP memory blocks 112 along with a proper control method.
The patent mentioned above discloses a method that utilizes a record element 150 outside the OTP memory area 110 to record the usage status of every OTP memory block 112. The control circuit 120 selects a proper OTP memory block 112 to program or read by reading the data stored in the record element 150.